Semiconductor memories such as static random access memory (“SRAM”) and dynamic random access memory (“DRAM”) are in widespread use. DRAM is very common due to its high density with a cell size typically between 6F2 and 8F2, where F is a minimum feature size. However, DRAM is relatively slow, having an access time commonly near 20 nanoseconds (“ns”). Although SRAM access time is typically an order of magnitude faster than DRAM, an SRAM cell is commonly made of four transistors and two resistors or of six transistors, thus leading to a cell size of approximately 60F2 to 100F2.
Others have introduced memory designs based on a negative differential resistance (“NDR”) cell, such as a thyristor-base memory cell, to minimize the size of a conventional SRAM memory. A thyristor-based random access memory (“RAM”) may be effective in memory applications. Additional details regarding a thyristor-based memory cell are described in U.S. Pat. Nos. 6,891,205 B1 and 7,460,395 B1.
Charge leakage out of a thyristor-based memory cell negatively impacts the restore rate of such cell. Additional details regarding periodically pulsing a thyristor-based memory cell to restore or refresh state of such a cell may be found in Patent Cooperation Treaty (“PCT”) International Publication WO 02/082504.
Operation of an array of thyristor-based memory cells consumes power. Accordingly, it would be desirable and useful to provide an array of thyristor-based memory cells that consumes less power.